10. CACHE Instructions
10.22 Index Store Data (S)
Index Store Data (S) stores a quadword of data and 10 check bits into the secondary cache data array. It stores a doubleword of data from CP0 TagHi and TagLo and pads the remaining doubleword with zeroes. This allows the ECC and parity, which are based on the quadword, to be valid for the doubleword of data stored. The address of the quadword stored is defined by the PA of the CACHE instruction, and the way is defined by PA[0]. The data stored in the non-padded doubleword comes from CP0 TagHi and TagLo. The check bits are stored from ECC[9:0]. The tag array including the MRU bit is left unchanged.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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